Binary Logic Lab: Gates and a Half Adder
Change binary inputs and compare gate outputs, a half adder, and complete truth tables.
Free, with no sign-up.
For High school students and adults reviewing the topic.
About 8 minutes.
How does it work?
- Change the controls or open a named preset. Read the outputs, then check a challenge.
What will you get?
Compare the model’s outputs and check two challenges.
What does the model assume?
- Inputs and outputs are ideal binary values, either 0 or 1. Voltage thresholds and propagation delays are not modeled.
- NOT uses input A; input B has no effect for that selection. Both B rows remain visible in the table.
- Output is the gate’s result bit, or the sum bit for the half adder. Carry is defined for the half adder only.
Which setup would you like to try?
What can you change?
Range: 0 to 1 bit.
Range: 0 to 1 bit.
What does the model predict?
| Quantity | Value | Unit |
|---|---|---|
| Output or sum | 0 | bit |
| Carry | Not used by this gate |
Wire labels give the bits. The dotted wire is the half adder’s carry output.
| A | B | Output | Carry | Input row |
|---|---|---|---|---|
| 0 | 0 | 0 | Not used by this gate | Other inputs |
| 0 | 1 | 0 | Not used by this gate | Other inputs |
| 1 | 0 | 0 | Not used by this gate | Current inputs |
| 1 | 1 | 1 | Not used by this gate | Other inputs |
Can you reach these targets?
Find inputs that make NAND output 0.
- Target: Output or sum = 0 bit; tolerance 0 bit.
- Gate or circuit (NAND)
Find inputs that give a half-adder carry of 1 and a sum of 0.
- Target: Carry = 1 bit; tolerance 0 bit.
- Target: Output or sum = 0 bit; tolerance 0 bit.
- Gate or circuit (Half adder)